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Overview
Sistolic has developed a set of RTL(Verilog/VHDL) reusable code for
Ethernet switch applications. It includes all Ethernet MAC's, Switch
Engine, Multiple Queue Engine, Traffic Managers for various QoS algorithms,
Search Engines, SIP4-2,
10GBase_X/R/W PHY's, Wireless 802.11e a/b/g. All of our IP modules
are licensable for your application. The
IP’s will dramatically speed up the development effort and manage the
cost of producing new ASICs.
For enquiries: e-mail to: sales@sistolic.com
Deliverables with any IP license in single/multiple use:
1.
RTL
Source Code (VHDL/VERILOG)
2.
Summary
Documentation
3.
User
Manual
4.
Detailed
Implementation Guide
5.
FPGA
Netlist (if required)
6.
Test-Bench
(VHDL | SystemC)
7.
Test-Bench
Documentation
8.
Test
Plan
9.
Test
Suites (Regression & Coverage)
10.
One
Year Maintenance
11.
One
day free training
12.
On
going support
In addition to Intellectual Property licensing, Sistolic is a
"Private Label" developer of custom ASICs. We offer high quality
front-end ASIC Design Services at low cost and aggressive schedule. We can
take customer requirements (MRD, PRD, specification) and develop complete
product specifications and then deliver RTL code, Test-Bench, Documentation
under your or our project management. In addition we can support full
integration, verification and testing. Using customer modules (IP’s)
and/or our own modules (IP’s), Sistolic is capable of handling large
Front-End Designs, Verification and Documentation. We will guaranty
protections of customers IP/solution.
Also we will do customization of our IP’s
to your requirements. We will integrate our IP’s with your IP’s
in any design.
We offer IP’s as reusable code or module or we
offer IP’s in a product version. An IP offered as a product might contains
multiple IP’s as cores or macros. An aggregator or a switch IP might
contains multiple MAC’s IP, Multi Queue Engine IP, SPI4 interface
etc.
Designs
Sistolic
offers reusable IP cores and custom design services and will mix and match
as necessary to accommodate customer needs. The modular design of the cores
facilitates easy customization to include customer requirements. The
efficient design allows multiple implementations on a single die to reduce
power and cost. For each part there is a detailed and comprehensive
specification, theory of operation document, a clearly explained and
modeled user interface and a programmable compliant test-bench.
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